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W83626F/W83626D/W83626G LPC TO ISA BRIDGE SET
Table of Contents1. 2. 3. 4. 5. GENERAL DESCRIPTION ......................................................................................................... 2 FEATURES ................................................................................................................................. 2 BLOCK DIAGRAM OF W83626F/G............................................................................................ 3 PIN CONFIGURATION OF W83626F/G .................................................................................... 4 PIN DESCRIPTION..................................................................................................................... 5 5.1 W83626F/G PIN DESCRIPTION.................................................................................... 5
5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 LPC Interface ...................................................................................................................5 ISA Interface Signals ........................................................................................................6 K/B , GPIO AND 80h PCS# Function ...............................................................................9 Clock Buffer and Generator............................................................................................10 Power Signals ................................................................................................................10 Power-on strapping Signals............................................................................................10
6.
CONFIGURATION REGISTER................................................................................................. 11 6.1 6.2 6.3 1 Chip (Global) Control Register................................................................................... 11 Enable the following configuration registers by writing 26h to the location 4Eh twice. 11 CR03 (ROM Decoder Register, Default, 100011s0b) .................................................. 11
7. 8. 9.
PACKAGE DIMENSIONS 1 FOR W83626F (128-PIN PQFP) ................................................. 22 PACKAGE DIMENSIONS 2 FOR W83626D (128-PIN LQFP) ................................................. 22 REVISION HISTORY ................................................................................................................ 23
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Publication Release Date: May 25, 2005 Revision A1
W83626F/W83626D/W83626G
1. GENERAL DESCRIPTION
W83626F/W83626D/W83626G is a transparent LPC-to-ISA bus conversion IC. For the new generation Intel chipset Camino and Whitney, SiS Super South 960, featuring LPC bus, there is no support for ISA bus and slots. However, the demand of ISA devices still exists. For such case, W83626F/G is the best companion solution for the non-ISA chipset. Also the packages of W83626F/G had been chosen to be the most economic solution for save the M/B board layout size and cost. For the new generation chipset featuring LPC interface and support no ISA bus, W83627HF/HG (Winbond LPC I/O) together with the set of W83626F/G is the complete solution.
2. FEATURES
LPC to ISA Bridge
* * * * * * * * * * * * * * Meet LPC Spec. 1.1 Support LDRQ# (LPC DMA), SERIRQ (serial IRQ) Full ISA Bus Support except ISA Bus Masters, 16 bit I/O and Memory R/W 5V ISA and 3.3V LPC interfaces All Software Transparent IRQ Serializer for ISA Parallel IRQ transfer to Serial IRQ Supports 3 fully ISA Compatible Slots without Buffering LPC Bus at 33MHz Supports Programmable ISA Bus Divide the PCI Clock into 3 or 4 All ISA Signals can be Isolated 14.318MHz in to generate two 14.318MHz buffer out and one 24.576MHz Specific Keyboard Functions supported Support 8 programmable general purpose I/O pins Supports Configuration registers for programming performance
Package
* 128-pin PQFP for W83626F
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W83626F/W83626D/W83626G
3. BLOCK DIAGRAM OF W83626F/G
LFRAM# PCIRST# LAD[3:0] PCICLK LDRQ# SERIRQ LPC Interface ISA Interface
ISOLATE#
Signal Isolation Control
SA[19:0] SD[15:0] BALE AEN IOCHRDY IOCS16# IOCHK# IOR# IOW# LA[23:17] SBHE# MEMCS16# MEMR# MEMW# SMEMR# SMEMW# ZEROWS# MASTER# REFRESH# ROMCS# RSTDRV SYSCLK IRQ[3:7,9:12,14,15] DRQ[0:3,5:7] DACK[0:3,5:7]
3.3V 5V
Power SuppIy
14.318M
CLOCK GEN. / BUF.
14MOUT1 14MOUT2 24.576M
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Publication Release Date: May 25, 2005 Revision A1
W83626F/W83626D/W83626G
4. PIN CONFIGURATION OF W83626F/G
LA23 LA22 VCC5 LA21 LA20 LA19 LA18 GND LA17 MEMR# MEMW# SD8 SD9 SD10 SD11 SD12 SD13 VCC5 SD14 SD15 MASTER#/RTCEN DRQ7 GND DACK7# DRQ6 DACK6#/HEFRAS
103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
SBHE# BALE TC DACK2# IRQ3 IRQ4 IRQ5 GND IRQ6 IRQ7 SYSCLK REFRESH# DRQ1 DACK1# DRQ3 DACK3# IOR# VCC5 IOW# SMEMR# SMEMW# OWS# GND DRQ2 IRQ9 RSTDRV IOCHCK# SD7 SD6 SD5 SD4 SD3 VCC5 SD2 SD1 SD0 GPIO7/IOHCS# GPIO6/RTCCS# 11 199 9 9 999 99 9 88 888888 8877 77 777 7 7 766 66 6 00 0 9 8 7 6 5 43 21 0 98 7 65432 1 098 7 6 5 4 3 2 1 0 9 8 76 5 210 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 GPIO5/IRQ8 GPIO4/PLED GPIO3/IRQIN IOCHRDY GND AEN SA19 SA18 SA17 VCC5 SA16 SA15 SA14 SA13 GND SA12 SA11 SA10 SA9 VCC5 SA8 SA7 SA6 SA5 GPIO2/MCCS# GPIO1/KBCS#
W83626F LPC to ISA
1 1 1 1 1 1 1 1 1 12 2 2 2 22 2 2 2 2 3 3 3 3 3 3 33 3 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 90 1 2 3 45 6 7 8 9 0 1 2 3 4 5 67 8
DRQ5 DACK5# DRQ0 DACK0# VCC5 IRQ14 IRQ15 IRQ12 IRQ11 IRQ10 IOCS16# MEMCS16# LFRAM# PCIRST# GND LAD3 LAD2 LAD1 LAD0 VCC3 PCICLK LDRQ# SERIRQ PWRDN# AVCC3 14.318M 14MOUT1 14MOUT2 24.576M AGND SA0 SA1 SA2 SA3 SA4 80PCS#/KBEN# ROMCS# GPIO0/IRQ1
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W83626F/W83626D/W83626G
5. PIN DESCRIPTION
I/O12t I/O24t I/O12tp3 I/O24tp3 I/OD12t I/O24t OUT12 OUT24 O12p3 O24p3 OD12 OD24 INcs INt INtd INtu INts INtsp3 - TTL level bi-directional pin with 12 m A source-sink capability - TTL level bi-directional pin with 24 m A source-sink capability - 3.3V TTL level bi-directional pin with 12 m A source-sink capability - 3.3V TTL level bi-directional pin with 24 m A source-sink capability - TTL level bi-directional pin open drain output with 12 m A sink capability - TTL level bi-directional pin with 24 m A source-sink capability - TTL level output pin with 12 m A source-sink capability - TTL level output pin with 24 m A source-sink capability - 3.3V TTL level output pin with 12 m A source-sink capability - 3.3V TTL level output pin with 24 m A source-sink capability - Open-drain output pin with 12 m A sink capability - Open-drain output pin with 24 m A sink capability - CMOS level Schmitt-trigger input pin - TTL level input pin - TTL level input pin with internal pull down resistor - TTL level input pin with internal pull up resistor - TTL level Schmitt-trigger input pin - 3.3V TTL level Schmitt-trigger input pin
5.1 W83626F/G PIN DESCRIPTION
5.1.1 LPC Interface
PIN I/O FUNCTION SYMBOL
LAD[3:0] LFRAME#
16-19 13
I/O12tp3 INtsp3
These signal lines communicate address, control and data information over the LPC bus between a host and a peripheral. Indicates start of a new cycle or termination of a broken cycle. PCICLK provides timing for all transactions on the LPC bus. All LPC signals are sampled on the rising edge of PCICLK, and all timing parameters are defined with respect to this edge. Reset signal. It can connect to PCIRST# signal on the host. Serial IRQ Input/Output. Encoded DMA Request signal. Power Down. The signal is active low according to CR 44 Bit 7and wake-up enable by hardware setting. There are eight different power-down states (Power down Mode 3).
PCICLK PCIRST# SERIRQ LDRQ# PWRDN#
21 14 23 22 24
INt INtsp3 I/OD12t O12tp3 INtu
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Publication Release Date: May 25, 2005 Revision A1
W83626F/W83626D/W83626G
5.1.2 ISA Interface Signals
PIN I/O FUNCTION
SYMBOL
SA[19:17]
58-56
OUT24
System Address Bus. These are the upper address lines that define the ISA's byte granular address space (up to 1 M byte). SA [19:17] are at an unknown state upon PCIRST#. System Address Bus. These are the bi-directional lower address lines that define the ISA's byte granular address space (up to 1 M byte). SA [16:0] is at an unknown state upon PCIRST#.
54-51 SA[16:0] 49-46 44-41 35-31 122-121 SD[15:0] 119-114 75-71 69-67 AEN 59 OUT24 I/O24t I/O24t
System Data. SD [15:0] provides the 16-bit data path for devices residing on the ISA Bus. W83626F/G tri-states SD [15:0] during PCIRST#. Address Enable. AEN is asserted during DMA cycles. This signal is also driven high during W83626F/G initiated refresh cycles. AEN is driven low upon PCIRST#. I/O Read. IOR# is the command to an ISA I/O slave device that the slave may drive data on to the ISA data bus (SD [15:0]). I/O Write. IOW# is the command to an ISA I/O slave device that the slave may latch data from the ISA data bus (SD [15:0]). I/O Channel Ready. Resources on the ISA Bus negate IOCHRDY to indicate that additional time (wait states) is required to complete the cycle. ISA System Clock. SYSCLK is the reference clock for the ISA bus. The SYSCLK is generated by dividing PCICLK by 3 or 4. Reset Drive. W83628F asserts RSTDRV to reset devices that reside on the ISA Bus. The W83628F asserts this signal while the PCIRST# is asserted. 16-bit I/O Chip Select. This signal is driven by I/O devices on the ISA Bus to indicate that they support 16-bit I/O bus cycles. Memory Chip Select 16. MEMCS16# asserted indicates that the memory slave supports 16-bit accesses. I/O Channel Check. IOCHK# can be driven by any resource on the ISA bus during on detection of an error.
IOR#
86
I/O24t
IOW#
84
I/O24t
IOCHRDY SYSCLK
61 92
I/O24t OUT24
RSTDRV IOCS16# MEMCS16# IOCHCK#
77 11 12 76
OUT24 INt INt INt
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W83626F/W83626D/W83626G
ISA Interface Signals, continued
SYMBOL
PIN
I/O
FUNCTION
OWS#
81
INt
Zero Wait States. An ISA slave asserts ZEROWS# after its address and command signals have been decoded to indicate that the current cycle can be executed as an ISA zero wait state cycle. ZEROWS# has no effect during 16-bit I/O cycles. Unlatched Address. The LA [23:17] address lines are bi-directional. These address lines allow accesses to physical memory on the ISA Bus up to 16 Mbytes. LA [23:17] are outputs when the W83628F owns the ISA Bus. Standard Memory Write. SMEMW# asserted indicates the current ISA bus cycle is a memory write cycle to an address below 1 Mbyte. Standard Memory Read. SMEMR# asserted indicates the current ISA bus cycle is a memory read cycle to an address below 1 Mbyte. Refresh. REFRESH# asserted indicates that a refresh cycle is in progress, or that an ISA master is requesting W83626F/G to generate a refresh cycle. Upon PCIRST#, this signal is tri-stated. Bus Address Latch Enable. BALE is an active high signal asserted by the W83626F/G to indicate that the address (SA [19:0], LA [23:17]) and SBHE# signal lines are valid. The LA [23:17] address lines are latched on the trailing edge of BALE. BALE remains asserted throughout DMA and ISA master cycles. BALE is driven low upon PCIRST#. System Byte High Enable. SBHE# asserted indicates that a byte is being transferred on the upper byte (SD [15:8]) of the data bus. SBHE# is at an unknown state upon PCIRST#. Memory Read. MEMR# asserted indicates the current ISA bus cycle is a memory read. Memory Write. MEMW# asserted indicates the current ISA bus cycle is a memory write. MASTER#. This signal is used with a DREQ line by an ISA master to gain control of the ISA Bus.
103-104 LA[23:17] 106-109 111 SMEMW# 82 OUT24 I/O24t
SMEMR#
83
OUT24
REFRESH#
91
OUT24
BALE
101
OUT24
SBHE#
102
OUT24
MEMR# MEMW# MASTER#
112 113
I/O24t I/O24t
123 RTCEN# IRQ3 IRQ4 98 97
INt RTC Function Enable. The pin applies a pull-down resistor (4.7K ohm) to enable RTC functions ( RTCCS#, and IRQ8) INt INt Parallel Interrupt Requested Input 3. Parallel Interrupt Requested Input 4.
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Publication Release Date: May 25, 2005 Revision A1
W83626F/W83626D/W83626G
ISA Interface Signals, continued
SYMBOL
PIN
I/O
FUNCTION
IRQ5 IRQ6 IRQ7 IRQ9 IRQ10 IRQ11 IRQ12 IRQ14 IRQ15 DRQ0 DRQ1 DRQ2 DRQ3 DRQ5 DRQ6 DRQ7 DACK0# DACK1# DACK2# DACK3# DACK5# DACK6# HERFRA
96 94 93 78 10 9 8 6 7 3 90 79 88 1 127 124 4 89 99 87 2
INt INt INt INt INt INt INt INt INt INt INt INt INt INt INt INt OUT24 OUT24 OUT24 OUT24 OUT24
Parallel Interrupt Requested Input 5. Parallel Interrupt Requested Input 6. Parallel Interrupt Requested Input 7. Parallel Interrupt Requested Input 9. Parallel Interrupt Requested Input 10. Parallel Interrupt Requested Input 11. Parallel Interrupt Requested Input 12. Parallel Interrupt Requested Input 14. Parallel Interrupt Requested Input 15. DMA Request 0. The DREQ signal indicates that either a slave DMA device is requesting DMA services, or an ISA bus master is requesting use of the ISA bus. DMA Request 1. DMA Request 2. DMA Request 3. DMA Request 5. DMA Request 6. DMA Request 7. DMA Acknowledge 0. The DACK# signal indicates that either a DMA channel or an ISA bus master has been granted the ISA bus. DMA Acknowledge 1. DMA Acknowledge 2. DMA Acknowledge 3. DMA Acknowledge 5. DMA Acknowledge 6. During power-on reset, this is pulled-hi internally (Select 4Eh) and is defined as HEFRAS which provides the power-on value for CR3 bit4. A 4.7k ohm is recommended if intends to pull down. (Select 2Eh) DMA Acknowledge 7. Terminal Count. The W83628F asserts TC to DMA slaves as a terminal count indicator.
128
I/OD24t
DACK7# TC
126 100
OUT24 OUT24
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W83626F/W83626D/W83626G
5.1.3 K/B, GPIO AND 80h PCS# Function
PIN I/O FUNCTION
SYMBOL
80PCS# KBEN#
36
I/OD12t
80h PORT Chip Select.(Default) Only decode IO address port 80h and must apply with IOW#. K/B Functions Enable. During power-on reset this pin is weak pulled-up internally. The pin applied a pull-down resistor (4.7K ohm) to enable K/B functions. (IRQ1,KBCS#,and MCCS#)
ROMCS#
37
I/OD12t
ROMCS#, this pin enable positive decoder of BIOS address range [depend on CR03, bit 1 or external weak pulled-up during PCIRST is asserted]. General purpose I/O pin 0. Parallel Interrupt Requested Input 1. This interrupt request is used for specific K/B functions.
GPIO0 IRQ1 GPIO1 KBCS# GPIO2 MCCS# GPIO3 IRQIN GPIO4 PLED GPIO5 IRQ8 GPIO6 RTCCS# GPIO7 IOHCS#
38
I/OD12t
39
I/O12t
General purpose I/O pin 1. Decode the address 60h and 64h to output chip selected signal. Enable by KBEN# power-on setting.
40
I/OD12t
General purpose I/O pin 2. Decode the address 62h and 66h to output chip selected signal Enable by KBEN# power-on setting
62
I/OD12t
General purpose I/O pin 3. Programmable parallel IRQ input transfers to serial IRQ Enable by KBEN# power-on setting
63 64
I/OD12t I/OD12t
General purpose I/O pin 4. Power LED output, this signal is low after system reset. General purpose I/O pin 5. Parallel Interrupt Requested Input 8. This interrupt request is used for specific RTC functions. Enable by RTCEN# power-on setting
65
I/OD12t
General purpose I/O pin 6. Decode the address 70h and 71h to output chip selected signal Enable by RTCEN# power-on setting
66
I/OD12t
General purpose I/O pin 7. Decode SA [15-11] is all 0 and setting by CR04 Bit 6.
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Publication Release Date: May 25, 2005 Revision A1
W83626F/W83626D/W83626G
5.1.4 Clock Buffer and Generator
PIN I/O FUNCTION
SYMBOL
14.318M 14MOUT 1 14MOUT 2
26 27 28
INt OUT12t OUT12t
Main 14.318 MHz Clock Input. 14.318 MHz Buffer Output 1. 14.318 MHz Buffer Output 2. This pin is weak pull-up during 3 VDD ramp-up period. The default setting is 24.576 MHz and selected 25.000 MHz by external pull-down with 4.7K ohm (recommended) during power ramp-up period. 24.576 MHz Clock Output for Audio Codec or selected 25.000 MHz Clock Output for LAN on board solution.
24.576M 25.000M
29
OUT12t
5.1.5
Power Signals
PIN I/O FUNCTION
SYMBOL
VCC5 VCC3 GND AVCC3 AGND
5, 45, 55, 70, 85, 105, 120, 20 15, 50, 60, 80, 95, 110, 125 25 30
PWR PWR PWR PWR PWR
Digital 5V Supply. Digital 3.3V Supply. Digital Ground. Analog 3.3V Supply. Analog Ground.
5.1.6
Power-on strapping Signals
SYMBOL PIN I/O FUNCTION
80PCS#/KBEN#
36
I/OD12t
Power-on strapping with pulled-down register will enable K/B and mouse functions. When it is set, pin 38, 39 and 40 will do IRQ1, KBCS# and MCCS# signals. If there is a boot-ROM (BIOS), the signal must power-on with a weak pulled-high register. Power-on strapping with pulled-down register will enable RTC functions. When it is set, pin 64 and 65 will do IRQ8 and RTCCS# signals. Set this function will change the port that is used to access configuration-registers. Default setting is 4Eh, but by power-on strapping with a pulled-down register change to 2Eh.
ROMCS#
37
I/OD12t
MASTER/RTCEN#
123
INt
DACK6#/HEFRAS
128
I/OD24t
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W83626F/W83626D/W83626G
6. CONFIGURATION REGISTER
6.1 1 Chip (Global) Control Register
Enable the following configuration registers by writing 26h to the location 4Eh twice. Change the location to 2Eh by setting bit4 of CR03 or power-on strapping with a pulled-down register on pin 128. CR03 (ROM Decoder Register, Default, 100011s0b)
Bit 7-5 Bit4
Reserved. Configure Address and Value
= 0 Write 26h to the location 4E twice. (4Eh and 4Fh are index and data port) = 1 Write 26h to the location 2E twice (By DACK6 power-on setting with weak pull-down resistor).(The pair are 2Eh and 2Fh)
Bit 3-2
BIOS Decode Range of High Memory.
= 00 1MB BIOS ROM positive decode. = 01 2MB BIOS ROM positive decode. = 10 4MB BIOS ROM positive decode. = 11 8MB BIOS ROM positive decode. (Default setting)
Bit 1
BIOS ROM decoder Enable.
= 0 Disable BIOS ROM decoder. (Default setting) =1 Enable BIOS ROM decoder.
Bit 0
BIOS Protected Mode.
=0 BIOS Write Disable. (Default setting) =1 BIOS Write Enable. This bit set to "1" for updated BIOS used allow Memory R/W to the range of BIOS decoded. This bit is always set to "0" after reset.
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Publication Release Date: May 25, 2005 Revision A1
W83626F/W83626D/W83626G
CR04 (GPIO Status Register, Default 0ss00sssb)
If the GPIO is selected GPIO function, it will be controlled by CR10, 13, 14, 15, and 16.The pins were set non-GPIO functions by power-on setting pin or software programmed. Bit 7(GPIO7): = 1 Signal used as IOHCS# (Set by software only) = 0 Signal used as GPIO function (Default) Bit 6 (GPIO6): = 1 Signal used as RTCCS# (Set by pin123 RTCEN#) = 0 Signal used as GPIO function (Default) Bit 5 (GPIO5): = 1 Signal used as IRQ8 (Set by Pin 123 RTCEN#) = 0 Signal used as GPIO function (Default) Bit 4 (GPIO4): = 1 Signal used as PLED (Set by software only and programmed by CR CR17 bit [5, 4]) = 0 Signal used as GPIO function. (Default) Bit 3 (GPIO3): = 1 Signal used as IRQIN (depended on CR17 bit [3, 0]) = 0 Signal used as GPIO function (Default) Bit 2 (GPIO2): = 1 Signal used as MCCS# (decode address 62h and 66h) By Pin 36 KBEN# power-on setting = 0 Signal used as GPIO function (Default) Bit 1 (GPIO1): = 1 Signal used as KBCS# (decode address 60h and 64h) By Pin 36 KBEN# power-on setting = 0 Signal used as GPIO (Default) Bit 0 (GPIO0): = 1 Signal used as IRQ1 by Pin 36 KBEN# power-on setting = 0 Signal used as GPIO (Default)
CR05 (System Clock Register, Default 0x4D)
Bit 7
SYSCLK Divider
= 0 SYSCLK is equal to PCICLK divided by 4. = 1 SYSCLK is equal to PCICLK divided by 3.
Bit 6
8-bit I/O Recovery Enable
= 0 Disable bit [5:3] setting and uses 3.5 SYSCLKs for 8 bit I/O recovery time. = 1 Enable bit [5:3] setting.
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W83626F/W83626D/W83626G
Bit 5:3
8-bit I/O Recovery Times
When bit 6= 1, these 3 bits field define the additional number of SYSCLKs added to standard 3.5 SYSCLK recovery time for 8 bit I/O = 000 0 SYSCLK = 001 1 SYSCLK = 010 2 SYSCLKs = 011 3 SYSCLKs = 100 4 SYSCLKs = 101 = 110 = 111 5 SYSCLKs 6 SYSCLKs 7 SYSCLKs
Bit 2
= 0 Ignore bits [1:0] setting and uses 3.5 SYSCLKs for 16-bit I/O recovery time. = 1 The 16-bit I/O recovery time is decided by bits 1:0.
Bit 1:0
16-bit I/O Recovery Times.
When bit 2 = 1 , this 2-bit field defines the additional number of SYSCLKs added to standard 3.5 SYSCLK recovery time for 16 bit I/O = 01 1 SYSCLK = 10 2 SYSCLKs = 11 3 SYSCLKs = 00 4 SYSCLKs
CR10 (GPIO0-GPIO7 Function Enable Register, Default 0x00)
Bit 7 - 1: Reserved. Bit 0:
GPIO Function Activity.
= 1 All GPIO functions are activated. All registers (CR 11, 12, 13, 14, 15, 16) about GPIO function will be set default value . = 0 All GPIO functions are inactive except the signals by power-on setting. If any one of CR04 bit [7, 0] was set non-GPIO function, the bit just affect set GPIO function .
CR11, CR12 (Reserved Register for GPIO Control without Configure Mode Entry) The register is programmable when the bit 0 of CR10 is set to "1 "and affected by the settings of CR14 (I/O Selection) and CR16 (Inversion).
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Publication Release Date: May 25, 2005 Revision A1
W83626F/W83626D/W83626G
User defines port address to control GPIO functions. To control GPIO state without entry configure mode. SA [0..7] can be defined on the bit [0..7] of CR11 and SA [8..15] on the bit [ 0..7] of CR12. For example: Define address 50h in CR11 and 01h in CR12 after reset. bit 0= -GPIO0 (=0 low state, =1 Hi state) bit 1=-GPIO1 (=0 low state =1 Hi state) ,bit 2=GPIO2,.........,bit 7=GPIO7 the same definition as bit 0. Set CR14 to "00h "(output port) and CR16 to " 00h " (incoming/outgoing) -o 150 aa ------(10101010) b indicated GP7,GP5,GP3 and GP1 are Hi state. -o 150 55 ------(01010101) b indicated GP6,GP4,GP2,and GP0 are Hi state. - i 150 ------show all states of GPIO[7..0]
CR13 (GPIO0-GPIO7 Address Decoder Rester, Default 0x00)
The register is programmable when the bit 0 of CR10 is set to " 1 ". Bit 7:
Address Decoder 2
=1 Enable address decoder .Generate a CS# signal to GPIO port which decided by bit[6..4] ,the specify address in CR34 and CR35 and mask range in CR 33. =0 Disable address decoder.
Bit 6 -Bit 4:
Address Decoder 2 Output Selection.
Define which GP port as address decoder depended on CR33, CR34 and CR35. = 000 Selected GPIO 0 as CS# = 001 Selected GPIO 1 as CS# = 010 Selected GPIO 2 as CS# = 011 Selected GPIO 3 as CS# = 100 Selected GPIO 4 as CS# = 101 Selected GPIO 5 as CS# = 110 Selected GPIO 6 as CS# = 111 Selected GPIO 7 as CS# output output output output output output output output
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W83626F/W83626D/W83626G
Bit 3:
Address Decoder 1
=1 Enable address decoder. Generate a CS# signal to GPIO port which decided by bit[6..4] ,the specify address in CR31 and CR32 and mask range in CR 30.
=0 Disable address decoder.
Bit 2 -Bit 0:
Address Decoder 1 Output Selection.
Define which GP port as address decoder depend on CR30,CR31 and CR32. = 000 Selected GPIO 0 = 001 Selected GPIO 1 = 010 Selected GPIO 2 = 011 Selected GPIO 3 = 100 Selected GPIO 4 = 101 Selected GPIO 5 = 110 Selected GPIO 6 = 111 Selected GPIO 7 as CS# as CS# as CS# as CS# as CS# as CS# as CS# as CS# output output output output output output output output
CR14 (GPI0-GPIO7 I/O Selection Register, Default 0xFF) The register is programmable when the bit 0 of CR10 is set to "1 ".
Bit [7..0] are corresponding with GPIO [7..0] . When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port.
CR15 (GPIO0-GPIO7 Data Register, Default 0x00) The register is programmable when the bit 0 of CR10 is set to "1 ".
Bit [7..0] are corresponding with GPIO [7..0] . If a port is programmed to be an output port, then its respective bit can be read / written. If a port is programmed to be an input port, then its respective bit can only be read.
CR16 (GPIO0-GPIO7 Inversion Register, Default 0x00) The register is programmable when the bit 0 of CR10 is set to "1".
Bit [7..0] are corresponding with GPIO [7..0] . When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register.
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Publication Release Date: May 25, 2005 Revision A1
W83626F/W83626D/W83626G
CR17 (Power LED & IRQIN Control Register, Default 0x00)
Bit 7 -6: Reserved Bit 5 -4: =00 Power LED pin is tri-stated. =01 Power LED pin is driven low. =10 Power LED pin is a 1Hz toggle pulse with 50 duty cycle. =11 Power LED pin is a 1/4 Hz toggle pulse with 50 duty cycle. Bit 3 - 0: These bits select IRQ resource for IRQIN. Four bits transfer the decimal value to octal system. For example: Bit [3..0] = 1001b = 0x9h means IRQ 9 be selected. Bit [3..0] = 1100b = 0xCh means IRQ12 be selected
CR20 (Chip ID Register 1, Default 0x62)
Bit 7 - 0:DEVIDB7 - DEBIDB0 --> Device ID Bit 7 - Bit 0 = 0x 62(read only).
CR21 (Chip ID Register 2, Default 0x6x)
Bit 7 - 0: DEVREVB7 - DEBREVB0 --> Device Rev Bit 7 - Bit 0 = 0x61(read only). Bit [3..0] indicate the version of the chip.
CR30 (Mask Range of Address Decoder 1 Register, Default 0x00)
This register is used to mask address bits (A7~A0) for specify address decoder, if the corresponding bit of this register is set to a 1, the corresponding address bit (A7~A0) is ignore by the specify address decoder. For example: If the decoding range is 0x3F8 ~ 0x3FF, you can set 0x3F8 to CR 31, 32 and 07h to CR30.
CR31, 32 (Address Decoder 1 Specification Register, Default 0x00)
This register contains the address for specify decoder. CR 31 Bit [7..0] are used to define low byte of specify address. CR 32 Bit [7..0] are used to define high byte of specify address. For example: Decoding address was set to be 0x3F5h and write F5h to CR 31 and 03h to CR 32 .
CR33 ((Mask Range of Address Decoder 2 Register, Default 0x00)
This register is used to mask address bits (A7~A0) for specify address decoder, if the corresponding bit of this register is set to a 1, the corresponding address bit (A7~A0) is ignore by the specify address decoder. For example: If the decoding range is 0x3F8 ~ 0x3FF,you can set 0x3F8 to CR 34, 35 and 07h to CR33 . - 16 -
W83626F/W83626D/W83626G
CR34, 35 Address Decoder 2 Specification Register, Default 0x00)
This register contains the address for specify decoder. CR 34 Bit [7..0] are used to define low byte of specify address. CR 35 Bit [7..0] are used to define high byte of specify address. For example: Decoding address was set to be 0x3F5h and write F5h to CR34 and 03h to CR35. This register contains the address for specify decoder.
CR40 (Clock controllable Register, Default 0x00)
This register is used to enable clock power-down state of the chip. It will shut down 14.318MHz. Bit 7 -1: Reserved. Bit 0 : =1 Power down mode. When entry power down mode, clock output will be turn off. =0 Normal used.
CR41 (Clock tested Register, Reserved for Winbond internal test) CR42 (Tristate controllable Register (Power-down Mode1) , Default 0x1B)
Bit 7: REFRESH Cycles Tristated. Bit 6: SYSCLK Output Tristated. Bit 5: Address Signals Tristated Enable. Bit 4 - 0: Defined tristated address signals range.(See Table 1) For example: Define address Bit [4..0] = 0x10h SA [19..16] and LA [23..17] signals will be tristated. Table 1
SET VALUE(HEX) TRI_STATE RANGE WORKABLE
00 01 02
SA[19..0] and LA[23..17] SA[19..1] and LA[23..17] SA[19..2] and LA[23..17]
None one SA[0] SA[1..0]
. .
14 Set value(Hex)
. .
LA[23..17] Tri_state range
. .
SA[19..0] Workable
- 17 -
Publication Release Date: May 25, 2005 Revision A1
W83626F/W83626D/W83626G
Table 1, continued.
SET VALUE(HEX)
TRI_STATE RANGE
WORKABLE
. .
1A 1B
. .
LA[23] None one
. .
SA[19..0] and LA[22..17] SA[19..0] and LA[23..17]
CR43 (Tristate controllable Register (Power-down Mode2), Default 0x07)
The Fast mode is used to improve the performance of transferable interface, because some applications will do fast transaction. To set the suitable bits to decide on specify range or all ISA cycles will meet the requested I/O cycles. Bit 7: Bit 6: Reserved. = 1 Enable Fast mode by ADDRESS DECODER 2 and SYSCLK is depended on the state of Bit 3 . = 0 ADDRESS DECORDER 2 doesn't affect Fast Mode and do original operation. Bit 5: = 1 Enable Fast mode by ADDRESS DECODER 1 and SYSCLK is depended on the state of Bit 3. = 0 ADDRESS DECORDER 1 doesn't affect Fast Mode and do original operation. Bit 4: = 1 Enable Fast Mode of whole chip, whole ISA cycle of this bridge will be done Fast Mode operation and SYSCLK is depended on the state of Bit 3. = 0 Normal operation, just Bit 6 and Bit 5 can affect Fast Mode operation. Bit 3: = 1 SYSCLK is equal to PCICLK divided by 1 when decoding range is in Fast Mode. = 0 SYSCLK is equal to PCICLK divided by 2 when decoding range is in Fast Mode. Bit 2: = 1 Disabled Memory cycles. = 0 Normal used. Bit 1: = 1 Forced 16 bit cycles. = 0 Normal used. Bit 0: = 1 8-bit data bus decode only. Only SD [7..0] signals are active. = 0 Normal used.
- 18 -
W83626F/W83626D/W83626G
CR44 (Tristate controllable Register (Power-down Mode3) , Default 0x07)
Bit 7: =1 Enable Power-down functions.(ISOLATE# was power-on setting.) =0 Normal used. Bit 6: Bit 5: Reserved. =1 SA10 is set as mask (ignored) bit in ADDRESS DECODER 2. The function is used to improved the performance of ECP mode of LPT. If the decoding range is 0x378-0x37F and 0x778-0x77F ,you can set this bit to 1 for Fast Mode operation. = 0 Normal operation. Bit 4: =1 SA10 is set as mask (ignored) bit in ADDRESS DECODER 1. The function is used to improved the performance of ECP mode of LPT. If the decoding range is 0x378-0x37F and 0x778-0x77F ,you can set this bit to 1 for Fast Mode operation. = 0 Normal operation. Bit 3: SERIRQ POWER DOWN SELECT. =1 When the chip is in power down mode, the SERIRQ block is inactive. =0 When the chip is in power down mode, the SERIRQ block is active. Bit 2 -0: Set SYSCLK divided ratio.(2,4,8,16,32,64) = 000 Disable Power-down Mode3. = 001 SYSCLK divided by 2. = 010 SYSCLK divided by 4. = 010 SYSCLK divided by 4 = 011 SYSCLK divided by 8 = 100 SYSCLK divided by 16 = 101 SYSCLK divided by 32 = 110 SYSCLK divided by 64 = 111 LPC I/F,all clocks and signals will be tristated.
- 19 -
Publication Release Date: May 25, 2005 Revision A1
W83626F/W83626D/W83626G
CR45 (Wake-Up Event Register, Default 0x01)
Bit 7: =0 Normal used. =1 Wake up from power-down mode by IRQ 7 occurred. Bit 6: =0 Normal used. =1 Wake up from power-down mode by IRQ 6 occurred. Bit 5: =0 Normal used. =1 Wake up from power-down mode by IRQ 5 occurred. Bit 4: =0 Normal used. =1 Wake up from power-down mode by IRQ 4 occurred. Bit 3: =0 Normal used. =1 Wake up from power-down mode by IRQ 3 occurred. Bit 2: Bit 1: Reserved. =0 Normal used. =1 Wake up from power-down mode by IRQ 1 occurred. Bit 0: =0 Normal used. =1 Wake up from power-down mode by rising edge of ISOLATE# signal occurred.
CR46 (Wake-Up Event Register, Default 0x00)
Bit 7 -5: Reserved Bit 4: =0 Normal used. =1 Wake up from power-down mode by IRQ 12 occurred. Bit 3: =0 Normal used. =1 Wake up from power-down mode by IRQ 11 occurred. Bit 2: =0 Normal used. =1 Wake up from power-down mode by IRQ 10 occurred. Bit 1: =0 Normal used. =1 Wake up from power-down mode by IRQ 9 occurred. Bit 0: =0 Normal used. =1 Wake up from power-down mode by IRQ 8 occurred.
- 20 -
W83626F/W83626D/W83626G
CR48 (DMA CYCLES FAST MODE SELECT, Default 0x00) (Write only)
The Fast mode is used to improve the performance of transferable interface, because some applications will do fast transaction. To set the suitable bits to decide on specify range or all ISA cycles will meet the requested DMA cycles. Bit 7: = 0 Normal used. = 1 The DMA cycles of channel 7 is in fast mode. Bit 6: = 0 Normal used. = 1 The DMA cycles of channel 6 is in fast mode. Bit 5: = 0 Normal used. = 1 The DMA cycles of channel 5 is in fast mode. Bit 4: Bit 3: Reserved. = 0 Normal used. = 1 The DMA cycles of channel 3 is in fast mode. Bit 2: = 0 Normal used. = 1 The DMA cycles of channel 2 is in fast mode. Bit 1: = 0 Normal used. = 1 The DMA cycles of channel 1 is in fast mode. Bit 0: = 0 Normal used. = 1 The DMA cycles of channel 0 is in fast mode.
- 21 -
Publication Release Date: May 25, 2005 Revision A1
W83626F/W83626D/W83626G
7. PACKAGE DIMENSIONS 1 FOR W83626F (128-PIN PQFP)
HE E
102 65
Symbol Min
Dimension in mm
Dimension in inch
Nom
0.35 2.72 0.20 0.15 14.00 20.00 0.50
Max
0.45 2.87 0.30 0.20 14.10 20.10
Min
0.010 0.101 0.004 0.004 0.547 0.783
Nom
0.014 0.107 0.008 0.006 0.551 0.787 0.020
Max
0.018 0.113 0.012 0.008 0.555 0.791
103
64
D
HD
128
39
1
e
b
38
A1 A2 b c D E e HD HE L L1 y 0
c
0.25 2.57 0.10 0.10 13.90 19.90
17.00 23.00 0.65
17.20 23.20 0.80 1.60
17.40 23.40 0.95
0.669 0.905 0.025
0.677 0.913 0.031 0.063
0.685 0.921 0.037
0.08 0 7 0
0.003 7
Note:
1.Dimension D & E do not include interlead flash. 2.Dimension b does not include dambar protrusion/intrusion . 3.Controlling dimension : Millimeter 4.General appearance spec. should be based on final visual inspection spec.
A A2 See Detail F Seating Plane A1 y
L L1 Detail F
5. PCB layout please use the "mm".
8. PACKAGE DIMENSIONS 2 FOR W83626D (128-PIN LQFP)
HE E
102 65
Symbol Min
Dimension in mm
Dimension in inch
Nom
----1.40 0.16 ----14.00 20.00 0.40 BSC 16.00 ----22.00 0.60 1.00
Max
0.15 1.45 0.23 0.20 14.10 20.10 ------------0.75
Min
0.002 0.053 0.005 0.004 0.547 0.783 ------------0.018
Nom
---0.055 0.006 ----0.551 0.787 0.016 0.630 0.866 0.024 0.039
Max
0.006 0.057 0.009 0.008 0.555 0.791 ------------0.030
103
64
D
HD
128
39
1
e
b
38
A1 A2 b c D E e HD HE L L1 y 0
c
0.05 1.35 0.13 0.10 13.90 19.90 ------------0.45
0.08 0 7 0
0.003 7
A A2 See Detail F Seating Plane A1 y
L L1 Detail F
Note: 1.Dimension D & E do not include interlead flash. 2.Dimension b does not include dambar protrusion/intrusion . 3.Controlling dimension : Millimeter 4.General appearance spec. should be based on final visual inspection spec.
5. PCB layout please use the "mm".
- 22 -
W83626F/W83626D/W83626G
9. REVISION HISTORY
VERSION DATE PAGE DESCRIPTION
A1
May 25, 2005
23
ADD Important Notice
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
- 23 -
Publication Release Date: May 25, 2005 Revision A1

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